Electrically erasable and programmable flash memory of a conventional type is illustrated in FIG. 1 in a block form. The memory is disclosed in a data book, entitled "Flash Memory", published by SAMSUNG ELECTRONICS CO. Ltd, 3, 1998. As shown in FIG. 1, the flash memory includes an array 10 of electrically erasable and programmable memory cells, which are arranged at intersections of plural word lines and plural bit lines (not shown). One of the memory cells is schematically illustrated in FIG. 2. A memory cell of the electrically erasable and programmable flash memory comprises a cell transistor or a floating gate transistor, which has a source and a drain each formed in a p-type semiconductor substrate or a bulk, a floating gate formed over a channel region between the source and the drain with an insulator interposed therebetween, and a control gate formed over the floating gate with another insulator interposed therebetween.
The flash memory further comprises a row-address buffer & latch circuit 20, a column-address buffer & latch circuit 30, a pre decoder circuit 40, a row selector circuit 50, a column selector circuit 60. A row of memory cells in the array 10 is selected by the row selector circuit 50 according to address signals which are provided from the row-address buffer & latch circuit 20 via the pre decoder circuit 40. Columns of memory cells therein are selected by the column selector circuit 60 according to address signals which are provided from the column-address buffer & latch circuit 30 via the pre decoder circuit 40.
Each of the memory cells in the selected row and columns is programmed under the bias condition that a ground voltage (e.g., 0 V) is applied to its source and its substrate, a high voltage (e.g., +10 V from a program voltage generator 90) to its control gate, and a positive voltage (e.g., +5 V to +6 V) suitable to generate hot electrons to its drain. According to the bias condition, the sufficient amount of negative charges is accumulated in the floating gate and thereby the floating gate has (-) potential. This forces the threshold voltage of the programmed cell transistor to be increased during a read operation. During the read operation, a state of the memory cell is discriminated by a sense amplifier 110 as an "OFF" state, and its threshold voltage is distributed in a range of +7 V to +9 V, as shown in FIG. 3. The above-described program operation is performed under the control of a control logic & command register circuit 70.
As well known, the array 10 of the flash memory is divided into a plurality of sectors. The bulk regions of the respective sectors are electrically separated from each other, and memory cells integrated in each sector are simultaneously erased during an erase operation.
Each of memory cells in a selected selector is erased by the Fowler-Nordheim tunneling mechanism. According to the F-N tunneling mechanism, a negative high voltage (e.g., -10 V from an erase voltage generator 100) is applied to the control gate, a positive voltage (e.g., +5 V to +6 V) suitable to make the F-N tunneling is applied to the semiconductor substrate of the bulk, and the source and the drain are maintained at a floating state. The erase operation of such a bias condition is referred to as "Negative Bulk and Gate Erase" operation. By the bias condition, strong electric field of 6 to 7 MV/cm is made between the control gate and the semiconductor substrate. As a result, negative charges accumulated in the floating gate are discharged through the insulator having the thickness of about 100 .sub.66 (angstrom). This makes the threshold voltage of the erased cell transistor lowered during the read operation. During the read operation, a state of the memory cell is discriminated by the sense amplifier 110 as an "ON" state, and its threshold voltage is distributed in a range of +1 V to +3 V, as illustrated in FIG. 3. Similarly, the above-described erase operation is performed under the control of the control logic & command register circuit 70.
As well known in the art, a time required to erase memory cells in a sector and to program memory cells is longer than that required to read data from memory cells. For instance, an erase time is about one second, a read time is about 100 ns (nanosecond), and a program time is about 10 us (microsecond). In the flash memory is provided a suspend mode of operation in which an erase operation for a sector is suspended while a program or read operation for another sector can be performed. That is, the suspend mode of operation is provided to the flash memory as a system interrupt function. The suspended erase operation is resumed after completing the read or program operation for another sector.
In the flash memory is also provided a status read operation in order for an user to confirm its status of operation. The status of operation for the flash memory can be judged to use values of five data input/output pins DQ2, DQ3, DQ5, DQ6, and DQ7 or a value of a pin R/B#. The symbol # is to indicate an active low signal. During the status read operation, the values of the data input/output pins are changed as an output enable signal OE# is toggled in synchronization with a read timing. The statuses are as follows.
TABLE 1 Operation DQ7 DQ6 DQ5 DQ3 DQ2 R/B# Standard Mode Program DQ7# Toggle 0 N/A No 0 toggle Erase 0 Toggle 0 1 Toggle 0 Erase Suspend Mode Read within erase 1 No 0 N/A Toggle 1 suspended sector toggle Read within non- Data Data Data Data Data 1 erase suspended sector Erase suspend DQ7# Toggle 0 N/A N/A 0 program
In the table, a symbol N/A indicates "not available". As shown in the table, the values of the pins R/B#, DQ2, DQ3, DQ5, DQ6, and DQ7 are toggled or maintained at a previous value according to a mode of operation. As illustrated in FIG. 4, for example, when an erase operation is performed, the values of the pins DQ2 and DQ6 are toggled as the signal OE# is toggled. When an erase operation is suspended and then a read operation is performed, the value of the pin DQ2 is toggled while the value of the pin DQ6 is maintained at a previous state. As seen from the above description, the status read operation is performed by toggling the signal OE# after an input of a command for an erase/program operation.
FIG. 5 shows an output enable buffer illustrated in FIG. 1. The output enable buffer 130 is composed of a NOR gate G1 and two inverters INV1 and INV2 connected as illustrated in FIG. 5. When the output enable signal OE# is at a high level as an inactive state, output signals POE and OE have a low level, respectively. On the other hand, when the output enable signal OE# is at a low level as an active state, the signals PEO and OE have a high level, respectively.
In FIG. 6, a conventional data output circuit comprised in the circuit 122 is illustrated which is associated with a data input/output pin whose value is toggled in the synchronization with the output enable signal OE# during the status read operation. As seen from the table, the values of the pins DQ2 and DQ6 are toggled as the signal OE# is toggled during an erase operation. During the program operation, the value of the pin DQ2 is not toggled while the value of the pin DQ6 is toggled. In FIG. 6, the data output circuit associated with the pin DQ2 is illustrated, but that associated with the pin DQ6, whose value is toggled according to the signal OE#, is also configured the same as FIG. 6. The data output circuit 122 outputs a cell data signal from the sense amplifier 110 in FIG. 1 in synchronization with the signal POE during a normal read operation, and outputs a status data signal synchronized with the signal POE in response to the signal OE and a flag signal STATUS_EN during the status read operation. The flag signal STATUS_EN is activated high when a command associated with a program/erase operation except for a read operation is provided to the flash memory.
The data output circuit 122 includes a status data signal generator 124 which is composed of two inverters INV3 and INV4 and a S-R flip flop, a selector or a multiplexer 126 which is composed of two transmission gates TG1 and TG2, a PMOS transistor MP1 functioning as a pull-up transistor, a NMOS transistor MN1 functioning as a pull-down transistor, an inverter INV5, a NAND gate G2 for driving the pull-up transistor and a NOR gate G3 for driving the pull-down transistor, connected as illustrated in FIG. 6. The S-R flip flop has three inputs S, R and CLK and two outputs Q and Q#. The input S of the flip flop is directly coupled to its output Q#, and thereby the S-R flip flop functions as a D flip flop.
FIG. 7 is a timing diagram for describing a status read operation of the flash memory.
In operation, when the flag signal STATUS_EN is at a low level, that is at a normal read operation, the transmission gate TG1 is activated and the transmission gate TG2 is inactivated. A cell data signal CDS is transferred to first inputs of the gates G2 and G3 through the transmission gate TG1, respectively. If the signal CDS is at a low level, the pull-down transistor MN1 is turned on in synchronization with a low-to-high transition of the signal POE. If the signal CDS is at a high level, the pull-up transistor MP1 is turned on in synchronization with a low-to-high transition of the signal POE.
When the flag signal STATUS_EN is at a high level and the output enable signal OE# is toggled to read its status of operation, a status data signal SDS from of the status data signal generator 124 is toggled between a high level and a low level in synchronization with a rising edge of the signal OE from the OE buffer 130. In particular, whenever the signal OE transitions from a low level to a high level, the status data signal SDS is toggled from a low level to a high level or from a high level to a low level. Since the flag signal STATUS_EN is at a high level, the transmission gate TG1 is inactivated and the transmission gate TG2 is activated. The status data signal SDS from the status data signal generator 124 is transferred to the first inputs of the gates G2 and G3 through the transmission gate TG2, respectively. In a case where the signal POE is at a low level, the output pin DQ2/6 is maintained at a high impedance regardless of a logic level of a signal from the selector 126. On the other hand, when the signal POE is at a high level, a value of the output pin DQ2/6 is pulled up to a high level or down to a low level according to the logic level of the signal from the selector 126, that is, the status data signal SDS.
As can be seen from FIG. 7, the status data signal SDS transitions after a delay time t.sub.D from a low-to-high transition of the signal OE elapses. The delay time t.sub.D is about 5 ns (nanosecond) which is determined by a path from an output of the OE buffer 130 to an input of the driver G2 or G3. The delay time t.sub.D causes a racing problem between the signal POE and the status data signal SDS. As depicted by a dot line in FIG. 7, an abnormal period of the output signal DQ2/6 is generated owing to the racing between the signals POE and SDS. This results a power noise and an unnecessary power consumption. Such a power noise may affect an internal erase/program operation.
In general, since external loading of a data input/output pin is very large (e.g., 30 pF to 100 pF), a power noise (a power supply voltage or a ground voltage noise) is made at the value of the data input/output pin is toggled. As described above, such a power noise affects an internal erase/program operation. Therefore, it is preferable to minimize the number of toggled pins during the status read operation.
In FIG. 8, a data output circuit is illustrated which is not associated with the status read operation (or is reserved during the status read operation). The data output circuit 128 is composed of a PMOS transistor MP2 functioning as a pull-up transistor, a NMOS transistor MN2 functioning as a pull-down transistor, an inverter INV6, a NAND gate G4 for driving the pull-up transistor and a NOR gate G5 for driving the pull-down transistor, connected as illustrated in FIG. 8. The data output circuit 128 outputs a cell data signal CDS in response to the signal POE. When the status read operation is performed, that is, when the output enable signal OE# is toggled during an erase/program operation, a value of the pin coupled to the circuit 128 can be toggled by both a cell data signal CDS and the signal POE. Similarly, this causes a power noise and an unnecessary power consumption.